The ambition of SPIDER is to bring SW computing to TRL 5 by designing and realising a hybrid SW–CMOS computing system that interfaces with standard microelectronics. Therefore, the central objective of SPIDER is:
OBJ1: Demonstrate a hybrid SW–CMOS computing system: computation occurs via SW interference while input and output interfaces are implemented with conventional CMOS and microelectronic systems. The hybrid SW–CMOS system consists of several subsystems: the SW circuit itself, a mixed signal CMOS analog periphery integrated circuit (APIC), and an interposer to combine the SW circuits and the APIC into a single package. To achieve the main objective OBJ1, the objectives OBJ2, OBJ3, and OBJ4 must all be achieved.
OBJ2: Develop, design, and realise a SW circuit beyond a single MAJ3.
OBJ3: Develop, design, and realise a mixed signal CMOS APIC to drive and read out the SW circuit.
OBJ4: Develop, design, and realise a large bandwidth RF interposer to co-integrate the mixed signal CMOS APIC and the SW circuit into a single package. Realising objectives OBJ2 to OBJ4 will provide the building blocks for the system in the targeted OBJ1. Note that each of these subordinate objectives already exceeds the current state of the art. SPIDER aims to design and realise hybrid SW–CMOS computing systems that are as flexible as possible. The mixed signal CMOS APIC provides a generic set of outputs and inputs. It provides repeaters for electronic cascading as an alternative to the direct SW gates cascading. In parallel, a first implementation of the SW circuit will consist of an array of majority gates and inverters. In later stages, the SW circuit may also include cascaded logic gates. Within this approach, hybrid systems are then obtained by connecting inputs, outputs, and repeaters via the interposer. The actual logic circuits are formed during packaging, and the SW and mixed signal CMOS APIC can be utilised to create different logic functionality. Using this approach, SPIDER targets the realisation of an 8-bit adder as a concrete implementation. Reaching objectives OBJ2 to OBJ4 individually is however insufficient to achieve the main objective OBJ1, since the individual parts of the system must be mutually compatible and co-optimised by system-technology co-optimisation (STCO). Hence, SPIDER targets an additional objective OBJ5, which is central as it links objectives OBJ2 to OBJ4 together to reach objective OBJ1.
OBJ5: Co-optimise the technology of SW circuit, periphery CMOS circuit, and interposer to obtain a single operational system (STCO). This process will be reflected in the work plan and further detailed in the next section. The key document for this process will be a living system-technology co-specification and design (STCD) document for hybrid SW–CMOS systems, as further discussed in the next section. By reaching its objectives, SPIDER will demonstrate the feasibility of as well as provide a first experimental assessment of the performance of a hybrid SW–CMOS computing system at TRL 5. Based on the experimental results, SPIDER will then draft a roadmap for hybrid SW–CMOS computing systems that details the pathway to render hybrid SW–CMOS computing competitive with commercial CMOS.

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