Concept and Approach

SPIDER targets to realise a hybrid SW–CMOS computing system combining a SW circuit with a mixed signal CMOS APIC for SW excitation and readout in a single package using 2.5D interposer technology. To this aim, SPIDER will design and experimentally realise the individual components of the system: the SW circuit, the mixed signal CMOS APIC, as well as the interposer. None of the subcomponents have been demonstrated for applications in hybrid SW–CMOS computing systems and therefore SPIDER will develop methodologies for their design and realisation. Moreover, no system level understanding of such a hybrid system is presently available. A main task of SPIDER will therefore also be the development of the system-level understanding of hybrid SW–CMOS computing systems via STCO. The STCO actions will lead to the achievement of OBJ5 and enable the realisation of the hybrid system and the achievement of OBJ1. Since STCO is at the centre of SPIDER’s activities, this will be first described below, followed by the methodology to develop the individual subsystems and the packaging activities required to obtain the final hybrid system.

To optimise the final performance and minimise risks, the project will be pursued in two stages. In a first stage, SPIDER will assess simple systems of single gate and few cascaded gates systems. For this, a special APIC will be designed as well as a test interposer. This allows for a test of all components and the system integration at low complexity levels. We emphasise that the outcome of this stage will already be a demonstrator beyond the state of the art. For example, a packaged majority gate that interfaces with surrounding test electronics can be considered as a first demonstrator of a hybrid system and used, e.g., in communication actions via the scientific community and the general public. More on this topic can be found in Sec. 2. The second stage includes the realisation of the final targeted system, an 8-bit adder. These activities will build on the experience from stage 1. By then, much insight into the system integration and STCO has already been built up. This procedure allows for staged learning, minimising risk, and maximising the probability for a successful achievement of SPIDER’s objectives.

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